DESCRIPTION

· The 74ACT280 is a high-speed CMOS 9-bit parity generator/checker fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.

· It features nine data inputs (A to I) and odd/even parity outputs (ΣODD and ΣEVEN).

· The device generates either odd or even parity based on the number of high-level inputs, with ΣODD high for odd and ΣEVEN high for even.

· It is designed to interface directly with High-Speed CMOS, TTL, NMOS, and CMOS systems.

· All inputs and outputs are protected against static discharge with 2KV ESD immunity.

FEATURES

· High speed with tPD = 7ns (typical) at VCC = 5V.

· Low power dissipation: ICC = 4µA (max) at TA=25°C.

· TTL compatible with VIH = 2V (min) and VIL = 0.8V (max).

· 50Ω transmission line driving capability.

· Symmetrical output impedance: |IOH| = IOL = 24mA (min).

· Balanced propagation delays: tPLH ≅ tPHL.

· Operating voltage range: VCC (OPR) = 4.5V to 5.5V.

· Pin and function compatible with 74 Series 280.

· Improved latch-up immunity.

APPLICATIONS

· Suitable for high-speed CMOS systems requiring parity generation or checking.

· Can be used in systems interfacing with TTL, NMOS, and CMOS voltage levels.

· Ideal for applications needing static discharge protection with 2KV ESD immunity.

· Easily expandable word-length capability by cascading.