DESCRIPTION

· The 74HC280; 74HCT280 is a 9-bit parity generator or checker with both even and odd parity outputs.

· PE is HIGH when an even number of data inputs (I0 to I8) is HIGH.

· PO is HIGH when an odd number of data inputs are HIGH.

· Expansion to larger word sizes is possible by cascading up to nine devices.

· Inputs include clamp diodes for interfacing with voltages exceeding VCC.

FEATURES

· Generates odd or even parity for nine data bits.

· Wide supply voltage range: 2.0 to 6.0 V.

· CMOS level inputs for 74HC280; TTL level inputs for 74HCT280.

· Low power dissipation and high noise immunity.

· Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.

· Complies with JEDEC standards: JESD8C and JESD7A.

· ESD protection: HBM exceeds 2000 V; CDM exceeds 1000 V.

· Operating temperature range: -40 °C to +125 °C.

APPLICATIONS

· Parity generation and checking in digital systems.

· Data integrity verification in communication systems.

· Error detection in memory and storage systems.

· Cascading for larger word size parity operations.