DESCRIPTION

· The 74LVC2G17 is a dual buffer with Schmitt-trigger inputs that can be driven from either 3.3 V or 5 V devices, allowing use as translators in mixed 3.3 V and 5 V environments.

· It is fully specified for partial power down applications using I OFF, which disables the output to prevent damaging backflow current when powered down.

FEATURES

· Wide supply voltage range from 1.65 V to 5.5 V

· Overvoltage tolerant inputs to 5.5 V

· High noise immunity

· ±24 mA output drive (V CC = 3.0 V)

· CMOS low-power consumption

· Latch-up performance exceeds 250 mA

· Direct interface with TTL levels

· IOFF circuitry provides partial Power-down mode operation

· Compliance with JEDEC standards: JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD-8B/JESD36 (2.7 V to 3.6 V)

· ESD protection: HBM (ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V), CDM (ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V)

· Multiple package options

· Specified temperature range from -40 °C to +85 °C and -40 °C to +125 °C

APPLICATIONS

· Wave and pulse shapers for highly noisy environments