DESCRIPTION

· Monolithic Field Programmable System Level Integrated Circuit (FPSLIC) combining AT40K SRAM-based FPGA and Embedded High-performance RISC AVR Core.

· Includes extensive Data and Instruction SRAM and JTAG ICE.

· Features 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM.

· Supports 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM.

· High-performance DSP Optimized FPGA Core Cell with Dynamic In-System Reconfigurability.

· FPGA Configuration Access from AVR Microcontroller Core for Cache Logic Designs.

· Very Low Static and Dynamic Power Consumption, ideal for Portable and Handheld Applications.

FEATURES

· Patented AVR Enhanced RISC Architecture with 120+ Powerful Instructions, most Single Clock Cycle Execution.

· High-performance Hardware Multiplier for DSP-based Systems, Approaching 1 MIPS per MHz Performance.

· C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers.

· Low-power Idle, Power-save and Power-down Modes with 100 µA Standby and 2-3 mA per MHz Active.

· Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM.

· JTAG (IEEE std. 1149.1 Compliant) Interface with Extensive On-chip Debug Support.

· AVR Fixed Peripherals including Industry-standard 2-wire Serial Interface, Two Programmable Serial UARTs, and Timers/Counters.

· Support for FPGA Custom Peripherals with AVR Peripheral Control and FPGA Macro Library.

· Multiple Oscillator Circuits with Programmable Watchdog Timer and Software-selectable Clock Frequency.

· 3.3V 33 MHz PCI-compliant FPGA I/O with High-performance I/O Structures.

· High-performance, Low-power 0.35µ CMOS Five-layer Metal Process.

· State-of-the-art Integrated PC-based Software Suite including Co-verification.

APPLICATIONS

· Ideal for Portable and Handheld Applications due to Low Power Consumption.

· Suitable for DSP-based Systems with High-performance Hardware Multiplier.

· Effective in Systems requiring Dynamic In-System Reconfigurability.

· Applicable in designs needing Extensive On-chip Debug Support and JTAG Interface.

· Useful in applications requiring Custom Peripherals and FPGA Macro Library.

· Appropriate for Real-time Clock applications with Oscillator to Timer/Counter.