DESCRIPTION

· High-performance Fully CMOS, Electrically-erasable Complex Programmable Logic Device (CPLD)

· Advanced Digital CMOS Technology with 100% Testing and Complete Reprogrammability

· Available in Commercial and Industrial Temperature Ranges

· Offered in 44-lead and 100-lead TQFP Packages

FEATURES

· 64 Macrocells with 5.0 ns Pin-to-pin Propagation Delay

· Registered Operation up to 333 MHz

· Optimized for 1.8V Operation with Multi-voltage I/O Support (1.5V, 1.8V, 2.5V, 3.3V)

· In-System Programming (ISP) via IEEE 1532 (JTAG) Interface

· IEEE 1149.1 JTAG Boundary Scan Test Capability

· Flexible Logic Macrocell with Configurable Flip-flops and Expandable Product Terms

· Programmable Output Slew Rate and Open Collector Output Option

· Power Saving Options and Programmable Pin-keeper on Inputs and I/Os

· Programmable Schmitt Trigger and Input/I/O Pull-up Options

· Security Fuse Feature and Hot-Socketing Support

· Fully Green and RoHS Compliant

APPLICATIONS

· Suitable for high-speed logic integration and complex digital designs

· Ideal for applications requiring multi-voltage I/O interfaces

· Used in systems that benefit from in-system programmability and boundary scan testing

· Applicable in energy-sensitive applications due to low standby current and power-saving features