DESCRIPTION

· High-density, high-performance, electrically-erasable complex programmable logic device (CPLD) with 3.0V to 3.6V operating range.

· Features 128 macrocells, 5 product terms per macrocell (expandable to 40), and pin-to-pin delay of 15 ns.

· Supports registered operation up to 77 MHz with enhanced routing resources and flexible logic macrocell.

· Available in commercial and industrial temperature ranges with 84-lead PLCC, 100-lead PQFP/TQFP, and 160-lead PQFP packages.

FEATURES

· Advanced EE technology: 100% tested, completely reprogrammable, 10,000 program/erase cycles, 20-year data retention, 2000V ESD protection, and 200 mA latch-up immunity.

· Advanced power management: 5 µA standby for "L" version, pin-controlled 100 µA standby mode, programmable pin-keeper inputs, and reduced-power feature per macrocell.

· JTAG boundary-scan testing compliant with IEEE Std. 1149.1-1990 and 1149.1a-1993, fast in-system programmability (ISP) via JTAG, and PCI compliance.

· Security fuse feature, green (Pb/halide-free/RoHS compliant) package options, and improved connectivity with additional feedback routing and alternate input routing.

APPLICATIONS

· Suitable for high-performance logic designs requiring flexible and efficient routing resources.

· Ideal for applications needing advanced power management and low standby power consumption.

· Used in systems requiring JTAG boundary-scan testing and fast in-system programmability.

· Applicable in environments demanding high reliability, long data retention, and robust ESD protection.