DESCRIPTION

· High-density, high-performance fully CMOS electrically-erasable complex programmable logic device.

· Optimized for 1.8V operation with multi-voltage I/O support (1.5V, 1.8V, 2.5V, 3.3V).

· Available in 100-lead TQFP and 132-ball CBGA packages.

· Suitable for commercial and industrial temperature ranges.

FEATURES

· 128 macrocells with 5.0 ns pin-to-pin propagation delay.

· Registered operation up to 333 MHz with enhanced routing resources.

· Supports SSTL2 and SSTL3 I/O standards.

· In-system programming (ISP) via IEEE 1532 (JTAG) interface.

· IEEE 1149.1 JTAG boundary scan test capability.

· Flexible logic macrocell with D/T/Latch configurable flip-flops.

· Programmable output slew rate, open collector output, and pin-keeper options.

· Programmable Schmitt trigger input and pull-up options.

· Advanced digital CMOS technology with 10,000 program/erase cycles and 20-year data retention.

· Security fuse feature and hot-socketing support.

APPLICATIONS

· Ideal for high-performance digital logic designs requiring flexible and reprogrammable solutions.

· Suitable for multi-voltage I/O operations in complex electronic systems.

· Applicable in industrial and commercial environments with extended temperature ranges.