DESCRIPTION

· The Ultra37000™ family offers high-density CMOS CPLDs with superior system performance.

· Features a Programmable Interconnect Matrix (PIM) connecting multiple logic blocks.

· Each logic block includes a product term array, allocator, and 16 macrocells.

· Devices are electrically erasable and In-System Reprogrammable (ISR) via JTAG interface.

· Supports both 3.3V and 5V operations, with PCI compatibility and programmable bus-hold on all I/Os.

FEATURES

· ISR™ technology allows reconfiguration without altering pinout or timing.

· High density with 32 to 512 macrocells and 32 to 264 I/O pins.

· Simple timing model with no fanout, expander, or dedicated vs. I/O pin delays.

· Flexible clocking with four synchronous clocks per device and clock polarity control.

· Available in various packages from 44 to 400 leads, including lead-free options.

APPLICATIONS

· Ideal for high-performance programmable logic solutions in complex systems.

· Suitable for applications requiring frequent design changes without hardware modifications.

· Effective in systems needing compatibility with both 3.3V and 5V logic levels.

· Useful in PCI-compatible systems due to meeting electrical and timing requirements.

· Applicable in power-sensitive designs with 3.3V operation reducing power consumption.