DESCRIPTION

· The Ultra37000™ family offers high-density CMOS CPLDs with superior system performance.

· Designed for flexibility, ease of use, and high performance, similar to the 22V10 but in high-density CPLDs.

· Features a Programmable Interconnect Matrix (PIM) connecting multiple logic blocks, each with its own product term array, allocator, and 16 macrocells.

· All devices are electrically erasable and In-System Reprogrammable (ISR), simplifying design and manufacturing processes.

· ISR functionality is facilitated through a JTAG-compliant serial interface, allowing reconfiguration without altering pinout or timing.

· Compatible with the PCI Local Bus specification, meeting all electrical and timing requirements.

· Available in both 5V and 3.3V versions, supporting various I/O levels and reducing power consumption in 3.3V devices.

FEATURES

· In-System Reprogrammable™ (ISR™) CMOS CPLDs with a JTAG interface for reconfigurability.

· High density with 32 to 512 macrocells and 32 to 264 I/O pins.

· Five dedicated inputs including four clock pins.

· Simple timing model with no fanout delays, expander delays, or additional delays through PIM.

· Programmable bus-hold capabilities on all I/Os.

· Intelligent product term allocator providing 0 to 16 product terms to any macrocell, with individual steering and sharing among local macrocells.

· Flexible clocking options with four synchronous clocks per device and clock polarity control per logic block.

· Consistent package/pinout offering across all densities, simplifying design migration.

· Available in various packages from 44 to 400 leads, including PLCC, CLCC, PQFP, TQFP, CQFP, BGA, and Fine-Pitch BGA, with lead-free options.

APPLICATIONS

· Ideal for high-performance programmable logic solutions requiring flexibility and ease of use.

· Suitable for applications needing in-system reprogrammability without affecting pinout or timing.

· Perfect for systems requiring compatibility with PCI Local Bus specifications.

· Applicable in environments where power consumption needs to be minimized, especially with 3.3V devices.

· Useful in designs that benefit from programmable bus-hold capabilities and flexible clocking options.