DESCRIPTION

· The Ultra37000™ family offers high-density CMOS CPLDs with superior system performance.
· Features a Programmable Interconnect Matrix (PIM) connecting multiple logic blocks.
· Each logic block includes a product term array, allocator, and 16 macrocells.
· Supports In-System Reprogrammability (ISR) via JTAG interface, allowing design changes without altering pinout or timing.
· Compatible with PCI Local Bus specifications and includes programmable bus-hold on all I/Os.

FEATURES

· Available in 3.3V and 5V versions with PCI compatibility.
· High density ranging from 32 to 512 macrocells and 32 to 264 I/O pins.
· Simple timing model with no fanout or expander delays.
· Flexible clocking options with four synchronous clocks per device.
· Packages available from 44 to 400 leads in various formats including PLCC, PQFP, and BGA.

APPLICATIONS

· Ideal for high-performance systems requiring flexible and reprogrammable logic solutions.
· Suitable for applications needing consistent package/pinout across different densities.
· Effective in environments where power consumption and voltage tolerance are critical.
· Useful in systems that benefit from JTAG boundary scan and ISR capabilities.