DESCRIPTION

· The Ultra37000™ family of CMOS CPLDs offers high-density programmable logic solutions with superior system performance.
· Designed to extend the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs.
· Architecture includes logic blocks connected by a Programmable Interconnect Matrix (PIM), each with its own product term array, allocator, and 16 macrocells.
· Devices are electrically erasable and In-System Reprogrammable (ISR), simplifying design and manufacturing processes.
· ISR feature allows reconfiguration without altering pinout or timing, facilitated via a JTAG-compliant serial interface.
· Compatible with the PCI Local Bus specification and features programmable bus-hold capabilities on all I/Os.

FEATURES

· In-System Reprogrammable™ (ISR™) CMOS CPLDs with JTAG interface for reconfigurability.
· High density with 32 to 512 macrocells and 32 to 264 I/O pins.
· Simple timing model with no fanout, expander, or dedicated vs. I/O pin delays.
· Available in 3.3V and 5V versions, both PCI-compatible.
· Programmable bus-hold capabilities on all I/Os.
· Intelligent product term allocator providing 0 to 16 product terms to any macrocell.
· Flexible clocking with four synchronous clocks per device and clock polarity control per logic block.
· Consistent package/pinout offering across all densities, simplifying design migration.

APPLICATIONS

· Suitable for high-density programmable logic solutions requiring system performance and flexibility.
· Ideal for applications needing in-system reconfigurability without changing pinout or timing.
· Applicable in systems compatible with PCI Local Bus specifications.
· Useful in designs requiring programmable bus-hold capabilities on I/Os.
· Appropriate for environments where 3.3V or 5V operation is necessary.