DESCRIPTION

· The CY7B991V is a 3.3 V RoboClock® low-voltage programmable skew clock buffer designed to optimize timing in high-performance computer systems.

· It features eight individual drivers arranged in four pairs, each capable of driving 50Ω terminated transmission lines with minimal output skew and LVTTL logic levels.

· Integrated PLL allows cancellation of external load and transmission line delays, enabling output-to-output delays up to ±12 time units.

· Provides divide-by-two and divide-by-four functions for flexible clock system design, allowing distribution of low-frequency clocks multiplied at the destination.

FEATURES

· All output pair skew <100 ps typical (250 ps max).

· Operates from 3.75 MHz to 80 MHz with user-selectable output functions including skew up to 18 ns, inverted/non-inverted outputs, and frequency division/multiplication.

· Zero input to output delay with 50% duty cycle outputs.

· LVTTL outputs drive 50Ω terminated lines, operates from a single 3.3 V supply with low operating current.

· Available in a 32-pin PLCC package with low cycle-to-cycle jitter (100 ps typical).

APPLICATIONS

· High-performance computer systems requiring optimized clock timing.

· Systems needing minimal output skew and full-swing logic levels.

· Applications requiring flexible clock distribution with frequency multiplication or division capabilities.