DESCRIPTION

· 8G bits DDR4 SDRAM with various configurations: 1024M words x 8 bits and 512M words x 16 bits.

· Available in 78-ball and 96-ball FBGA packages, lead-free and halogen-free.

· Operates at JEDEC standard 1.2V power supply with VDD = 1.2V ± 0.06V and VPP = 2.5V +0.25V / -0.125V.

· Supports data rates up to 3200/2666Mbps.

· Features 16 or 8 internal banks depending on the product configuration.

· Interface type: Pseudo Open Drain (POD).

· Burst Length (BL) options: 8 and 4 with Burst Chop (BC).

· CAS Latency (CL) and CAS Write Latency (CWL) with multiple supported values.

· Includes auto precharge, auto-refresh, and self-refresh functionalities.

· Operating temperature ranges: 0°C to +95°C (Commercial) and -40°C to +95°C (Industrial).

FEATURES

· Double-data-rate architecture enabling two data transfers per clock cycle.

· 8 bits prefetch pipelined architecture for high-speed data transfer.

· Bi-directional differential data strobe (DQS and /DQS) for data capture.

· Differential clock inputs (CK_t and CK_c) with DLL alignment for DQ and DQS transitions.

· Data mask (DM) for write data-in at both rising and falling edges of the data strobe.

· Supports Write Cycle Redundancy Code (CRC) and programmable preamble for read and write.

· Programmable burst length with nibble sequential and interleave modes.

· Dynamic On Die Termination and two termination states (RTT_PARK and RTT_NOM).

· Asynchronous RESET pin and ZQ calibration support.

· Write Levelization, TCAR mode, LP ASR mode, and Command Address (CA) Parity mode.

· Per DRAM Addressability (PDA) and fine granularity refresh.

· Geardown Mode, Self Refresh Abort, and Maximum power saving mode.

· Banks Grouping with CAS to CAS latency for same or different bank group accesses.

· DMI pin support for write data masking and DBIdc functionality.

APPLICATIONS

· Suitable for high-performance computing systems requiring high-speed data transfer.

· Ideal for applications needing robust memory solutions in commercial and industrial temperature ranges.

· Used in systems that require advanced memory features like dynamic termination and power-saving modes.

· Applicable in environments where reliability and data integrity are critical, supported by CRC and parity modes.