DESCRIPTION

· The PI6CB18200 is a 2-output, very low power PCIe Gen1/Gen2/Gen3/Gen4 clock buffer.

· It fans out two 100MHz low power differential HCSL outputs from a reference input.

· Features individual OE pins for each output for easier power management.

· Utilizes Diodes' proprietary PLL design for very low jitter, meeting PCIe Gen1/Gen2/Gen3 requirements.

· Supports Ethernet applications with 50MHz or 125MHz via SMBus.

· Offers configurable slew rate and amplitude through strapping pins or SMBus for optimized performance.

FEATURES

· 1.8V supply voltage.

· HCSL input supports 100MHz, 50MHz, or 125MHz via SMBus.

· 2 differential low power HCSL outputs.

· Individual output enable for each output.

· Programmable slew rate and output amplitude for each output.

· Differential outputs blocked until PLL is locked.

· Configurable via strapping pins or SMBus.

· 3.3V tolerant SMBus interface.

· Very low jitter outputs: differential cycle-to-cycle jitter <50ps, differential output-to-output skew <50ps.

· PCIe Gen1/Gen2/Gen3/Gen4 compliant.

· Pb-free & Green packaging: 24-lead 4×4mm TQFN.

APPLICATIONS

· PCIe Gen1/Gen2/Gen3/Gen4 clock buffering.

· Ethernet applications with 50MHz or 125MHz support.

· Systems requiring low power and low jitter clock distribution.

· Configurable clock buffer for optimized board performance.