SiTime SIT92110AI

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  • Part Number:

    SIT92110AI

  • Manufacturer:

    SiTime

  • Category:

    Clock Buffers, Drivers

  • RoHs:

    rohs RoHS Compliant

  • Datasheet:

    pdf SIT92110AI_Datesheet

  • Description:

    -40C TO 85C, 32PIN, 5050, 1.8V-3

  • In stock 0
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Specifications
Type
Paramete
Type
Paramete
Mounting Type
Surface Mount
Output
LVCMOS
Qualification
-
Voltage - Supply
1.8V ~ 3.3V
Frequency - Max
250 MHz
Grade
-
Number of Circuits
3
Operating Temperature
-40°C ~ 85°C (TA)
Package / Case
32-VFQFN Exposed Pad
Ratio - Input:Output
3:10
Supplier Device Package
32-QFN (5x5)
Type
Fanout Buffer (Distribution)
Differential - Input:Output
Yes/No
Input
HCSL, LVCMOS, LVDS, LVPECL, SSTL, XTAL
Overview

DESCRIPTION



· The SiT92110 is a 10-output low-jitter clock fan-out buffer designed for high-frequency clock/data distribution.
· It features low impedance LVCMOS outputs capable of driving 50 Ω series or parallel terminated transmission lines.
· The buffer can select a clock input from primary, secondary, or crystal sources, which can be single-ended or fully differential.
· The selected clock is distributed to 10 LVCMOS output drivers.
· It operates with independent core and output supply voltages of 3.3 V/2.5 V/1.8 V and 3.3 V/2.5 V/1.8 V/1.5 V, respectively, without requiring supply sequencing.



FEATURES



· Additive jitter performance of 50 fs RMS.
· Typical output skew between clock outputs is 30 ps.
· Supports level translation with core supply voltages of 3.3 V/2.5 V/1.8 V and output supply voltages of 3.3 V/2.5 V/1.8 V/1.5 V.
· Inputs include primary, secondary, and crystal inputs, selectable via programming input select pins.
· Input clock receiver accepts LVPECL, LVDS, LVCMOS, SSTL, HCSL, and XTAL waveforms.
· Supports crystal frequencies from 8 MHz to 50 MHz, with crystal bypass mode allowing frequencies up to 250 MHz.
· Available in a 32-pin, 5mm x 5mm QFN package.



APPLICATIONS



· High-frequency clock and data distribution in low-jitter environments.
· Systems requiring precise clock synchronization with minimal skew.
· Applications needing flexible clock input options and level translation capabilities.

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