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NXP 74LVC573APW/AUJ
RoHS Compliant
74LVC573APW/AUJ_Datesheet
DESCRIPTION
· The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs.
· It features latch enable (LE) and output enable (OE) inputs.
· Inputs can be driven from either 3.3 V or 5 V devices, making it suitable for mixed voltage environments.
· Schmitt-trigger action at all inputs ensures tolerance to slower input rise and fall times.
· Fully specified for partial power down applications using IOFF.
FEATURES
· Wide supply voltage range from 1.2 to 3.6 V.
· Overvoltage tolerant inputs up to 5.5 V.
· CMOS low power consumption.
· Direct interface with TTL levels.
· IOFF circuitry enables partial power-down mode operation.
· High-impedance when VCC = 0 V.
· Flow-through pinout architecture.
· Complies with JEDEC standards: JESD8-7A, JESD8-5A, JESD8-C/JESD36.
· ESD protection: HBM exceeds 2000 V, CDM exceeds 1000 V.
· Operating temperature range from -40 °C to +125 °C.
APPLICATIONS
· Suitable for use in mixed 3.3 V and 5 V environments as voltage translators.
· Ideal for applications requiring partial power-down mode operation.
· Used in systems where high-impedance outputs are necessary.
· Applicable in environments requiring robust ESD protection.
· Suitable for use in a wide range of industrial and consumer electronics.
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