DESCRIPTION

· 12-Bit, 1 GSPS/500 MSPS JESD204B Dual Analog-to-Digital Converter

· Low power consumption analog core with 1.5 W per channel

· Wide full power bandwidth supports IF sampling up to 2 GHz

· Buffered inputs with programmable input termination

· Flexible serial port interface (SPI) for control

· Programmable fast overrange detection

· 9 mm × 9 mm 64-lead LFCSP package

· Pin compatible with AD9680 14-bit, 1 GSPS/500 MSPS dual ADC

FEATURES

· JESD204B (Subclass 1) coded serial digital outputs

· SFDR 79 dBFS at 340 MHz (1 GSPS), 85 dBFS at 340 MHz (500 MSPS)

· SNR 63.4 dBFS at 340 MHz (1 GSPS), 65.6 dBFS at 340 MHz (500 MSPS)

· ENOB = 10.4 bits at 10 MHz (1 GSPS)

· DNL = ±0.16 LSB; INL = ±0.35 LSB (1 GSPS)

· Noise density -151 dBFS/Hz (1 GSPS), -150 dBFS/Hz (500 MSPS)

· 1.25 V, 2.5 V, and 3.3 V dc supply operation

· Low swing full-scale input 1.34 V p-p typical (1 GSPS), 1.63 V p-p typical (500 MSPS)

· No missing codes

· Internal ADC voltage reference

· Flexible termination impedance 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential

· 95 dB channel isolation/crosstalk

· Amplitude detect bits for efficient AGC implementation

· Differential clock input

· Optional decimate by 2 DDC per channel

· Integer clock divide by 1, 2, 4, or 8

· Flexible JESD204B lane configurations

· Small signal dither

APPLICATIONS

· Communications diversity multiband, multi-mode digital receivers

· 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE

· Point-to-point radio systems

· Digital predistortion observation path

· General-purpose software radios

· Ultrawideband satellite receiver

· Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions)

· Digital oscilloscopes

· High-speed data acquisition systems

· DOCSIS 3.0 CMTS upstream receive paths

· HFC digital reverse path receivers