NXP CBTL02043BBQ,115

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  • Part Number:

    CBTL02043BBQ,115

  • Manufacturer:

    NXP

  • Category:

    Analog Switches - Special Purpose

  • RoHs:

    rohs RoHS Compliant

  • Datasheet:

    pdf CBTL02043BBQ,115_Datesheet

  • Description:

    IC MUX/DEMUX 2:1 PCI 20DHVQFN

  • In stock 0
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Specifications
Type
Paramete
Type
Paramete
On-State Resistance (Max)
6Ohm (Typ)
Package / Case
20-VFQFN Exposed Pad
Features
Bi-Directional, SATA
Switch Circuit
-
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 85°C (TA)
-3db Bandwidth
10GHz
Grade
-
Voltage - Supply, Single (V+)
3V ~ 3.6V
Voltage - Supply, Dual (V±)
-
Multiplexer/Demultiplexer Circuit
2:1
Number of Channels
2
Supplier Device Package
20-DHVQFN (4.5x2.5)
Applications
DisplayPort, PCIe, USB
Qualification
-
Overview

DESCRIPTION

· CBTL02043A/B is a 2 differential channel, 2-to-1 multiplexer/demultiplexer switch designed for USB 3.1, PCI Express Gen 3, and other high-speed serial interfaces.

· It features minimized impedance, low attenuation, and reduced channel-to-channel skew and crosstalk.

· CBTL02043A has input and output pins on opposite sides, suitable for edge connectors on motherboards.

· CBTL02043B has outputs on both sides, ideal for placement between connectors to multiplex differential signals.



FEATURES

· 2 bidirectional differential channels, 2:1 multiplexer/demultiplexer.

· Supports high-speed signal switching up to 10 Gbps.

· High bandwidth: 10 GHz at -3 dB.

· Low insertion loss: -0.5 dB at 100 MHz, -1.3 dB at 4 GHz.

· Low return loss: -13.5 dB at 4 GHz.

· Low crosstalk: -35 dB at 4 GHz.

· Low off-state isolation: -20 dB at 4 GHz.

· Low intra-pair skew: 5 ps typical.

· Low inter-pair skew: 35 ps maximum.

· VDD operating range: 3.3 V ±10%.

· Shutdown pin (XSD) for power-saving mode with standby current less than 1 µA.

· ESD tolerance: 2000 V HBM, 1000 V CDM.

· Available in DHVQFN20 package.



APPLICATIONS

· USB 3.1 and PCI Express Gen 3 interfaces.

· High-speed serial interface applications requiring low power and minimal signal degradation.

· Expansion of existing high-speed ports with optimized pinouts for various application layouts.



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