DESCRIPTION

· The CDCLVD110A is a programmable low-voltage 1:10 LVDS clock driver designed to distribute one pair of differential LVDS clock inputs to 10 pairs of differential clock outputs with minimal skew.

· It is specifically designed to drive 50-Ω transmission lines and features an improved start-up circuit that minimizes enabling time in both AC- and DC-coupled systems.

· The device operates within a temperature range of -40°C to 85°C and is available in 32-pin LQFP and VQFN packages.

FEATURES

· Low-output skew of less than 30ps (typical) for clock distribution applications.

· Distributes one differential clock input to 10 LVDS differential clock outputs.

· VCC range of 2.5V ±5% with a typical signaling rate capability of up to 1.1GHz.

· Configurable register (SI/CK) allows individual enabling or disabling of outputs and selection between CLK0 and CLK1 inputs.

· Full rail-to-rail common-mode input range with a receiver input threshold of ±100mV.

· Fail-safe I/O pins for VDD=0V (power down).

APPLICATIONS

· Suitable for general-purpose industrial, communication, and consumer applications.