DESCRIPTION

· The CDCLVD1213 is a clock buffer that distributes an input clock to 4 pairs of differential LVDS clock outputs with low additive jitter.

· It accepts LVDS, LVPECL, or CML inputs and includes a high-performance divider for one output (QD) with division ratios of 1, 2, or 4.

· Designed for driving 50-Ω transmission lines, it operates in a 2.5-V supply environment and supports a fail-safe function.

· The device is packaged in a small, 16-pin, 3-mm × 3-mm VQFN package and is characterized for industrial temperature ranges from –40°C to 85°C.

FEATURES

· 1:4 Differential Buffer with low additive jitter (<300-fs RMS in 10-kHz to 20-MHz).

· Low output skew of 20ps (Maximum) and selectable divider ratio (1, /2, /4).

· Universal input compatibility with LVDS, LVPECL, and CML.

· 4 LVDS outputs compliant with ANSI EIA/TIA-644A standard, supporting clock frequencies up to 800MHz.

· Device power supply range: 2.375 V to 2.625 V, with ESD protection exceeding 3-kV HBM and 1-kV CDM.

APPLICATIONS

· Telecommunications and Networking.

· Medical Imaging.

· Test and Measurement Equipment.

· Wireless Communications.

· General-Purpose Clocking.