DESCRIPTION

· The Ultra37000™ family offers high-density CMOS CPLDs with superior system performance.

· Designed to enhance flexibility, usability, and performance akin to the 22V10 in high-density CPLDs.

· Features a Programmable Interconnect Matrix (PIM) connecting multiple logic blocks, each with its own product term array, allocator, and 16 macrocells.

· Supports In-System Reprogrammability (ISR) via a JTAG-compliant interface, allowing design changes without altering pinout or timing.

· Compatible with PCI Local Bus specifications, meeting all electrical and timing requirements.

FEATURES

· Available in 3.3V and 5V versions with PCI compatibility.

· Features 32 to 512 macrocells and 32 to 264 I/O pins.

· Includes four synchronous clocks per device with clock polarity control per logic block.

· Programmable bus-hold capabilities on all I/Os.

· Intelligent product term allocator supports 0 to 16 product terms per macrocell with individual steering and sharing.

· Simple timing model eliminates fanout, expander, and dedicated vs. I/O pin delays.

· Offered in various packages from 44 to 400 leads, including lead-free options.

APPLICATIONS

· Ideal for applications requiring high-density programmable logic solutions.

· Suitable for systems needing in-system reconfigurability without impacting pinout or timing.

· Effective in environments requiring compatibility with PCI Local Bus specifications.

· Useful in designs that benefit from programmable bus-hold capabilities and flexible clocking options.