DESCRIPTION

· CY7C1163KV18 and CY7C1165KV18 are 1.8V Synchronous Pipelined SRAMs with QDR II+ architecture.

· Features separate read and write ports for concurrent transactions.

· Utilizes a common address bus with addresses latched on alternate rising edges of the input clock.

· Designed for high bandwidth with DDR interfaces on both ports.

FEATURES

· Supports 550-MHz clock for high bandwidth.

· Four-word burst architecture reduces address bus frequency.

· Double data rate (DDR) interfaces at 1100 MHz on read and write ports.

· Available in 2.5 clock cycle latency with DOFF asserted HIGH.

· Operates with one cycle read latency when DOFF is asserted LOW.

· Core VDD = 1.8V ± 0.1V; I/O VDDQ = 1.4V to VDD.

· Available in 165-ball FBGA package (13 × 15 × 1.4 mm).

· JTAG 1149.1 compatible test access port.

· Phase-locked loop (PLL) for accurate data placement.

APPLICATIONS

· High-speed data processing systems requiring concurrent read and write operations.

· Networking equipment where high bandwidth and low latency are critical.

· Systems utilizing DDR interfaces for efficient data transfer.

· Applications requiring full data coherency and most current data access.