DESCRIPTION

· Single receiver for high-speed interconnects using LVDS technology.
· Converts LVDS levels to LVTTL signal levels with a typical differential input threshold of 100 mV.
· Ideal for high-speed transfer of clock or data.

FEATURES

· Data rate greater than 400 Mbps.
· Operates with a 3.3 V power supply.
· Maximum pulse skew of 0.4 ns.
· Maximum propagation delay of 2.5 ns.
· Bus pin ESD (HBM) protection exceeds 10 kV.
· Power-off, over-voltage tolerant input and output.
· Fail-safe protection for open-circuit, non-driven, shorted, or terminated conditions.
· High-impedance output at VCC < 1.5 V.
· Meets or exceeds TIA/EIA-644 LVDS standard.
· 5-Lead SOT23 package for space efficiency.

APPLICATIONS

· High-speed data transfer systems.
· Clock distribution networks.
· LVDS-based communication interfaces.