DESCRIPTION

· The FIN1217 and FIN1215 convert 21-bit parallel LVTTL data into three serial LVDS data streams.

· The FIN1218 and FIN1216 convert three serial LVDS data streams back into 21-bit LVTTL data.

· A phase-locked transmit clock is transmitted alongside the data stream via a separate LVDS link.

· At 85MHz transmit clock frequency, the FIN1217 transmits 21 bits of LVTTL data at 595Mbps per LVDS channel.

· These chipsets address EMI and cable size issues in wide, high-speed TTL interfaces.

FEATURES

· Low power consumption.

· Supports shift clock frequencies from 20MHz to 85MHz.

· 50% duty cycle on the receiver's clock output.

· ±1V common-mode range around ~1.2V.

· Narrow bus reduces cable size and cost.

· High throughput of 1.785Gbps.

· Up to 595Mbps per channel.

· Internal PLL requires no external components.

· Compatible with TIA/EIA-644 specification.

· Available in 48-lead TSSOP packages.

APPLICATIONS

· High-speed data transmission systems.

· EMI-sensitive environments.

· Systems requiring reduced cable size and cost.

· Applications needing LVDS to LVTTL conversion.

· Environments with wide and high-speed TTL interfaces.