DESCRIPTION

· The MC100EP210S is a low skew 1-to-5 dual differential driver designed for LVDS clock distribution.

· It fans out LVDS or LVPECL input signals to five identical differential LVDS outputs.

· The device ensures low output-to-output skew through optimal design, layout, and processing.

· Internal 50Ω resistors are provided across the inputs.

· VTA and VTB pins are unconnected for LVDS inputs and connected to VTT (VCC - 2.0 V) for LVPECL inputs.

FEATURES

· Typical output-to-output skew: 20 ps.

· Typical device-to-device skew: 85 ps.

· Typical propagation delay: 550 ps.

· Temperature compensation in the 100 series.

· Maximum frequency > 1 GHz.

· Operating range: VCC = 2.375 V to 2.625 V with VEE = 0 V.

· Internal 50Ω input termination resistors.

· LVDS input/output compatibility.

· Pb-Free device in LQFP-32 and QFN32 packages.

APPLICATIONS

· Low skew LVDS clock distribution across backplanes or boards.

· High-speed clock signal distribution in communication systems.

· Precision timing applications requiring minimal skew.