DESCRIPTION

· The MC100EP809 is a low skew 2:1:9 differential clock driver designed for clock distribution.

· It accepts two clock sources via an input multiplexer, one differential HSTL and one differential LVPECL, both compatible with LVDS levels.

· The CLK_SEL pin, which is LVTTL, selects between the two clock inputs.

· The Output Enable (OE) is synchronous and LVTTL, ensuring outputs are only enabled/disabled when in a LOW state.

· The device guarantees low output-to-output skew and uses an open emitter architecture with 50 Ω termination to ground.

FEATURES

· Typical device-to-device skew of 100 ps and within-device skew of 15 ps.

· HSTL compatible outputs drive 50 Ω to GND with no offset voltage.

· Maximum frequency > 750 MHz and typical propagation delay of 850 ps.

· Fully compatible with Micrel SY89809L.

· PECL and HSTL mode operating range: VCCI = 3 V to 3.6 V, VCCO = 1.6 V to 2.0 V.

· Open input default state.

· Pb-Free and RoHS compliant.

APPLICATIONS

· Ideal for low voltage applications requiring precise clock distribution with low skew.

· Suitable for driving multiple outputs in backplane designs.

· Effective in systems requiring high-frequency clock signals with minimal skew.