DESCRIPTION

· The MC74VHC573/MC74VHCT573A is a high-speed CMOS octal latch with 3-state output, fabricated using silicon gate CMOS technology.

· It combines high-speed operation similar to Bipolar Schottky TTL with low power dissipation of CMOS.

· The device is controlled by a latch enable input and an output enable input, with outputs entering a high impedance state when the output enable is high.

· MC74VHC573 inputs are compatible with standard CMOS levels, while MC74VHCT573A inputs are compatible with TTL levels.

· MC74VHCT573A can be used as a level converter for interfacing 3.3 V to 5.0 V systems, providing full 5.0 V CMOS level output swings.

· The internal circuit includes a buffer output for high noise immunity and stable output, with inputs tolerating voltages up to 5.5 V.

· Output structures provide protection when VCC = 0 V, preventing device destruction due to supply voltage mismatch, battery backup, hot insertion, etc.

FEATURES

· High Speed: tPD = 4.5 ns (Typ) at VCC = 5.0 V (VHC), tPD = 7.7 ns (Typ) at VCC = 5.0 V (VHCT).

· Low Power Dissipation: ICC = 4.0 µA (Max) at TA = 25°C.

· High Noise Immunity: VNIH = VNIL = 28%.

· Power Down Protection.

· Balanced Propagation Delays.

· Designed for: 2.0 V to 5.5 V (VHC), 4.5 V to 5.5 V (VHCT).

· Low Noise: VOLP = 1.2 V (Max) (VHC), VOLP = 1.6 V (Max) (VHCT).

· Pin and Function Compatible with Other Standard Logic Families.

· Latchup Performance Exceeds 100 mA.

· ESD Performance: Human Body Model > 2000 V.

· Chip Complexity: 234 FETs or 58.5 Equivalent Gates.

· Pb-Free, Halogen Free/BFR Free, RoHS Compliant.

APPLICATIONS

· Level conversion between 3.3 V and 5.0 V systems.

· Interface between 5 V and 3 V systems.

· High-speed data latching in digital systems.

· Systems requiring low power dissipation and high noise immunity.

· Applications needing protection against supply voltage mismatch, battery backup, and hot insertion.