DESCRIPTION

· The NB3L8543S is a high-performance, low skew 1-to-4 LVDS Clock Fanout Buffer.
· It features a multiplexed input that can be driven by either differential or single-ended inputs.
· The CLK_SEL pin selects between differential CLK/CLK and PCLK/PCLK inputs.
· The CLK_EN pin synchronously enables/disables outputs to avoid runt clock pulses.

FEATURES

· Four Differential LVDS Output Pairs.
· Two Selectable Differential Clock Inputs.
· CLK/CLK supports LVPECL, LVDS, HCSL, SSTL, and HSTL.
· PCLK/PCLK supports LVPECL, LVDS, CML, and SSTL.
· Maximum Output Frequency: 650 MHz.
· Additive Phase Jitter, RMS: 50 fs (typical).
· Output Skew: 40 ps (maximum).
· Part-to-part Skew: 200 ps (maximum).
· Propagation Delay: 1.9 ns (maximum).
· Operating Range: VDD = 2.5 V ±5% or 3.3 V ±10%.
· Ambient Operating Temperature Range: -40°C to +85°C.
· TSSOP-20 Package.
· Pb-Free Devices.

APPLICATIONS

· High-speed clock distribution in communication systems.
· Clock buffering in data centers and networking equipment.
· Signal integrity enhancement in high-frequency applications.
· Synchronization in multi-clock domain systems.