DESCRIPTION

· The NB7V586M is a differential 1-to-6 CML Clock/Data Distribution chip with a 2:1 Clock/Data input multiplexer and an input select pin.

· It features internal 50Ω termination resistors and supports LVPECL, CML, or LVDS logic levels.

· The device operates with a 1.8V supply for inputs and core logic, and produces six identical differential CML outputs.

· Outputs are configurable in three banks, each powered by either 1.8V or 1.2V.

· The CML output structure provides 16mA differential current with 400mV output swings when externally terminated.

· Optimized for low skew and minimal jitter, it is suitable for high-speed applications up to 6GHz or 10Gb/s.

· Available in a 5x5mm 32-pin QFN package.

FEATURES

· Maximum input data rate > 10Gb/s typical.

· Data dependent jitter < 10ps.

· Maximum input clock frequency > 6GHz typical.

· Random clock jitter < 0.8ps RMS, max.

· Low skew 1:6 CML outputs, 20ps max.

· 2:1 multi-level mux inputs.

· 175ps typical propagation delay.

· 50ps typical rise and fall times.

· Differential CML outputs, 330mV peak-to-peak, typical.

· Operating range: VCC = 1.71V to 1.89V, VCCOx = 1.14V to 1.89V.

· Internal 50Ω input termination resistors.

· VREFAC reference outputs for rebias capacitor-coupled signals.

· QFN32 package, 5mm x 5mm.

· Ambient operating temperature: -40°C to +85°C.

· Pb-Free device.

APPLICATIONS

· SONET, GigE, Fiber Channel, Backplane clock/data distribution.

· High-speed data communication systems.

· Clock and data signal fanout in multi-channel systems.

· Signal translation and distribution in high-frequency applications.