DESCRIPTION

· The PCA9618 is a CMOS integrated circuit designed for Fast-mode Plus (Fm+) I2C-bus or SMBus buffering of SCL or SDA lines.
· It supports bidirectional buffering, enabling bus extensions up to 540 pF at 1 MHz or 4000 pF at lower speeds.
· Features include overvoltage tolerance on DATAA and DATAB pins, high-impedance when unpowered, and an internal glitch filter.
· It can delay the SDA path to provide effective data hold time, with a minimum propagation delay of 46 ns.
· The device operates within a voltage range of 2.2 V to 5.5 V and includes a static level offset on port B, while port A eliminates static offset voltage.

FEATURES

· Bidirectional buffering for I2C-bus or SMBus applications.
· Overvoltage tolerant DATAA and DATAB pins.
· Internal glitch filter to ignore rather than expand glitches.
· Static level offset on port B and no static offset on port A.
· Output pull-down on port B set at approximately 0.55 V, with an input threshold about 90 mV lower.

APPLICATIONS

· Extending I2C-bus systems by isolating bus capacitance.
· Providing effective data hold time in systems requiring SDA delay.
· Buffering in 1-wire bus systems or when the master's output is insufficient to drive the bus.
· Enabling star topography by connecting port A of multiple PCA9618s on a common bus.
· Series connection of multiple PCA9618s without offset voltage buildup.