DESCRIPTION

· The PCKEL14 is a low skew 1:5 clock distribution chip designed for low skew clock distribution applications.

· It can be driven by differential or single-ended ECL, or PECL input signal with positive power supplies.

· Operates in ECL or PECL mode with a voltage supply range of -2.375 V to -3.8 V (or 2.375 V to 3.8 V).

· Features a multiplexed clock input for distributing lower speed scan or test clock along with the high-speed system clock.

· Synchronous common enable (EN) ensures outputs are only enabled/disabled when already in the LOW state.

· Internal flip-flop is clocked on the falling edge of the input clock.

· VBB pin provides an internally generated voltage supply for single-ended conditions and AC-coupled inputs.

FEATURES

· 50 ps output-to-output skew at 3.3 V.

· Synchronous enable/disable function.

· Multiplexed clock input.

· ESD protection: > 2.5 kV HBM.

· Temperature compensation in the PCK series.

· PECL mode operating range: VCC= 2.375 V to 3.8 V, with VEE=0V.

· NECL mode operating range: VCC= 0 V, with VEE=-2.375 V to -3.8V.

· Internal 75 kΩ pull-down resistors on all inputs, plus a 37.5 kΩ pull-up on CLK.

· Q output defaults LOW with inputs open or at VEE.

· Meets or exceeds JEDEC spec EIA/JESD78 IC latch-up test.

· Moisture sensitivity level 1.

· Flammability rating: UL-94 code V-0 @ 1/8".

APPLICATIONS

· Low skew clock distribution in high-speed systems.

· Systems requiring multiplexed clock inputs for test or scan clocks.

· Applications needing synchronous enable/disable functionality.

· Environments requiring robust ESD protection and temperature compensation.