DESCRIPTION

· The PCKEP14 is a low skew 1-to-5 differential driver designed for clock distribution, accepting two clock sources via an input multiplexer.

· Supports ECL/PECL inputs in differential or single-ended mode (using VBB output) and HSTL inputs under PECL conditions.

· Ensures low output-to-output skew through optimal design, layout, and processing.

· Requires identical 50 Ω termination for differential outputs to maintain skew specifications.

· Features a synchronous common enable (EN) to avoid runt clock pulses during enable/disable transitions.

· Operates in PECL mode with a positive VCC supply, suitable for +3.3 V or +2.5 V systems.

FEATURES

· Device-to-device skew: 100 ps.

· Within-device skew: 25 ps.

· Typical propagation delay: 400 ps.

· Maximum frequency: > 2 GHz (typical).

· Includes temperature compensation.

· PECL and HSTL mode: VCC = 2.375 V to 3.8 V, VEE = 0 V.

· NECL mode: VCC = 0 V, VEE = -2.375 V to -3.8 V.

· LVDS input compatible.

· Open input default state.

APPLICATIONS

· High-performance clock distribution in +3.3 V or +2.5 V systems.

· Suitable for systems requiring low skew and high-frequency clock signals.

· Ideal for applications utilizing ECL, PECL, or HSTL signaling standards.