Key Features:

• Three independent DSPLLs™ supporting flexible SyncE/IEEE 1588 and SETS architectures.
• Ultra-low jitter of 100 fs typical (12 kHz to 20 MHz).
• Compliance with ITU-T G.8273.2 T-BC, ITU-T G.8262 (SyncE) EEC Options 1 & 2, ITU-T G.812 Type III, IV, and ITU-T G.813 Option 1.
• Input frequency range from 48 to 54 MHz for external crystal, and up to 250 MHz for REF clock.
• Output frequency range up to 718.5 MHz for differential and 250 MHz for LVCMOS.
• Pin or software controllable DCO on each DSPLL with typical resolution to 1 ppt/step.
• Programmable jitter attenuation bandwidth per DSPLL: 0.001 Hz to 4 kHz.
• Highly configurable output drivers: LVDS, LVPECL, LVCMOS, HCSL, CML.
• Core voltage: VDD 1.8 V ±5% and VDDA 3.3 V ±5%.
• Independent output supply pins: 3.3 V, 2.5 V, or 1.8 V.
• Built-in power supply filtering.
• Status monitoring: LOS, OOF, LOL.
• Serial Interface: I2C or SPI (3-wire or 4-wire).
• ClockBuilder Pro™ software tool simplifies device configuration.
• Pb-free, RoHS-6 compliant.
• Temperature range: –40 to +85 °C.

Applications:

• Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Option 1 & 2.
• Telecom Boundary Clock (T-BC) as defined by ITU-T G.8273.2.
• IEEE 1588 (PTP) slave clock synchronization.
• Stratum 3/3E, G.812, G.813 network synchronization.

Technical Specifications:

• Ordering Part Number: Si5348B-B05097-GMR
• Number of DSPLLs: 1, 2, 3
• Output Clock Frequency Range: 1 Hz to 718.5 MHz
• Package: 64-Lead 9x9 QFN
• RoHS-6, Pb-Free: Yes
• Temperature Range: –40 to 85 °C