DESCRIPTION

· Advanced Schottky devices for high-speed arithmetic or logic comparisons on 8-bit binary or two's complement words.
· Fully expandable to any number of bits without external gates.
· Cascading paths implemented with only a two-gate-level delay to reduce overall comparison times.
· Latch is transparent when P latch-enable (PLE) input is high; latched when PLE is low.
· PLE, P, and Q data inputs utilize pnp input transistors to reduce low-level current input requirement.
· SN54AS885 operates from -55°C to 125°C; SN74AS885 operates from 0°C to 70°C.

FEATURES

· Latchable P-Input Ports with Power-Up Clear.
· Choice of Logical or Arithmetic (Two’s Complement) Comparison.
· Data and PLE Inputs utilize pnp input transistors to reduce dc loading effects.
· Approximately 35% improvement in ac performance over Schottky TTL.
· Cascadable to n bits while maintaining high performance.
· 10% less power than STTL for an 8-bit comparison.
· Package options include Plastic Small-Outline (DW), Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs.

APPLICATIONS

· High-speed arithmetic or logic comparisons in digital systems.
· Temporary storage for P-data word in digital designs.
· Cascading for comparing words of longer lengths in multi-stage systems.