DESCRIPTION

· The SSTUH32866 is a 1.8 V configurable register designed for DDR2 memory modules with parity checking.

· It complies with the JEDEC JESD82-7 standard and adds a parity checking function.

· Configurable to 25-bit 1:1 or 14-bit 1:2 topologies, designated as Register A or B on DIMM.

· Accepts a parity bit from the memory controller, compares it with DIMM-independent data inputs, and indicates parity errors on the QERR pin.

· Packaged in a 96-ball LFBGA package (13.5 mm × 5.5 mm).

· Identical to SSTU32866 in function and performance, with higher-drive outputs for heavy load nets.

FEATURES

· Configurable register for DDR2 Registered DIMM applications.

· Higher output drive strength optimized for high-capacitive load nets.

· Configurable to 25-bit 1:1 or 14-bit 1:2 mode.

· Controlled output impedance drivers for optimal signal integrity and speed.

· Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation delay; 2.0 ns max. mass-switching).

· Supports up to 450 MHz clock frequency.

· Optimized pinout for high-density DDR2 module design.

· Chip-selects minimize power consumption by gating data outputs.

· Supports SSTL_18 data inputs.

· Checks parity on DIMM-independent data inputs.

· Partial parity output and input allow cascading of two SSTUH32866s for correct parity error processing.

· Differential clock (CK and CK) inputs.

APPLICATIONS

· DDR2 Registered DIMM applications.

· High-capacitive load nets, such as stacked DRAMs.

· High-density DDR2 module designs.