DESCRIPTION

· The SSTUH32866 is a 1.8 V configurable register designed for DDR2 memory modules with parity checking.

· It complies with the JEDEC JESD82-7 standard and adds a parity checking function.

· Configurable to 25-bit 1:1 or 14-bit 1:2 topologies, with the latter allowing designation as Register A or B on the DIMM.

· It checks parity by comparing the parity bit from the memory controller with the data received on the DIMM-independent D-inputs.

· Packaged in a 96-ball LFBGA package (13.5 mm × 5.5 mm).

· Identical to SSTU32866 in function but with higher-drive outputs for heavy load nets.

FEATURES

· Configurable register for DDR2 Registered DIMM applications.

· Higher output drive strength optimized for high-capacitive load nets.

· Configurable to 25-bit 1:1 or 14-bit 1:2 mode.

· Controlled output impedance drivers for optimal signal integrity and speed.

· Exceeds JESD82-7 speed performance with 1.8 ns max. single-bit switching propagation delay.

· Supports up to 450 MHz clock frequency.

· Optimized pinout for high-density DDR2 module design.

· Chip-selects minimize power consumption by gating data outputs.

· Supports SSTL_18 data inputs and checks parity on DIMM-independent data inputs.

· Allows cascading of two SSTUH32866s for correct parity error processing.

· Differential clock (CK and CK) inputs.

APPLICATIONS

· DDR2 Registered DIMM applications requiring parity checking.

· High-capacitive load net environments.

· High-density DDR2 module designs.