GENERAL DESCRIPTION

The Microchip LAN8700/LAN8700i is a low-power, industrial-grade (LAN8700i) analog interface IC designed for high-performance embedded Ethernet applications. It features variable I/O voltage and HP Auto-MDIX support. The LAN8700/LAN8700i can run from a single 3.3V supply thanks to its built-in 3.3V-to-1.8V linear regulator. For systems that already provide a 1.8V power plane, the linear regulator can be disabled to streamline the design.

100BASE-TX Transmit Data Flow

Architectural Overview

The LAN8700/LAN8700i integrates an encoder/decoder, scrambler/descrambler, wave-shaping transmitter, output driver, and a twisted-pair receiver with adaptive equalization and baseline wander (BLW) correction, along with clock and data recovery capabilities. It can be set up to work with either the Media Independent Interface (MII) or the Reduced Media Independent Interface (RMII).

This device meets IEEE 802.3-2005 standards (MII pins are tolerant up to 3.6V) and supports both standard and vendor-specific register functions. It includes a full-duplex 10BASE-T/100BASE-TX transceiver, supporting 10 Mbps (10BASE-T) on Category 3 or 5 unshielded twisted-pair cables, and 100 Mbps (100BASE-TX) on Category 5 unshielded twisted-pair cables.

Highlights

• Single-chip Ethernet Physical Layer Transceiver (PHY)
• ESD protection: ±8 kV HBM without external components
• Meets EN/IEC61000-4-2 ESD standards: ±8 kV contact, ±15 kV air discharge (tested independently)
• flexPWR® Technology for flexible power management
• LVCMOS I/O voltage range: 1.6 V to 3.6 V
• Built-in 3.3 V to 1.8 V regulator for optional single-supply operation; can be disabled if 1.8 V system supply is present
• Supports HP Auto-MDIX per IEEE 802.3ab
• Supports cable lengths over 150 meters
• Automatic polarity correction
• Latch-up tolerance exceeds 150 mA (per EIA/JESD 78, Class II)
• Energy detect and low-power standby modes
• Low operating current: 39 mA typical at 10BASE-T, 79 mA typical at 100BASE-TX
• Supports auto-negotiation and parallel detection
• Compatible with MII and RMII interfaces
• Compliant with IEEE 802.3-2005 standards; MII pins tolerate up to 3.6 V
• Supports standard and vendor-specific register functions
• Integrated DSP with adaptive equalizer
• Baseline wander (BLW) correction
• Low-profile 36-pin QFN RoHS-compliant package (6 × 6 × 0.9 mm)
• 4 LED status indicators
• Commercial temperature range: 0°C to 70°C
• Industrial temperature range: -40°C to 85°C (LAN8700i)

Applications

• Set-top boxes
• Network printers and servers
• LAN-on-motherboard solutions
• 10/100 PCMCIA and CardBus devices
• Embedded telecom systems
• Video recording and playback systems
• Cable modems and routers
• DSL modems and routers
• Digital video recorders (DVRs)
• Personal video recorders (PVRs)
• IP phones and video phones
• Wireless access points
• Digital televisions (DTVs)
• Digital media adapters and media servers
• Point-of-sale (POS) terminals
• Automotive networking systems
• Gaming consoles
• Security and surveillance systems
• Power over Ethernet (PoE) applications
• Access control systems

LAN8700/LAN8700i System Block Diagram

Hubs and switches with multiple integrated MACs and external PHYs often require a high pin count due to the number of pins needed for each MII interface, which can increase overall system cost.

LAN8700/LAN8700i System Block Diagram

The RMII interface is designed for switch-based ASICs or other embedded solutions where minimizing pin count is critical for Ethernet connectivity. RMII uses only 6 pins per MAC-to-PHY connection, plus a single shared reference clock, compared with 16 pins required by the MII interface.

The Microchip LAN8700/LAN8700i supports operation in RMII mode. For the latest RMII specifications, please contact your Microchip sales representative.

Throughout this document, references to the LAN8700/LAN8700i apply to both commercial and industrial temperature versions, whereas the LAN8700i specifically denotes the industrial temperature variant.

LAN8700/LAN8700I ARCHITECTURAL OVERVIEW

LAN8700/LAN8700I ARCHITECTURAL OVERVIEW

PIN CONFIGURATION

LAN8700/LAN8700i Package Pin-out Diagram and Signal Table

LAN8700/LAN8700i Package Pin-out Diagram and Signal Table

LAN8700/LAN8700i 36-Pin QFN Pinout

PIN DESCRIPTION

This section explains the function of each pin. Signals that start with a lowercase “n” are active low. For example, nRST indicates that the reset signal is active low.

3.1 I/O Signals

The buffer types shown in the TYPE column of the tables are as follows:

• I – Input. Digital LVCMOS levels.
• IPD – Input with internal pull-down. Digital LVCMOS levels.
• O – Output. Digital LVCMOS levels.
• OPD – Output with internal pull-down. Digital LVCMOS levels.
• I/O – Input or output. Digital LVCMOS levels.
• IOPD – Input or output with internal pull-down. Digital LVCMOS levels.
• IOPU – Input or output with internal pull-up. Digital LVCMOS levels.
• AI – Analog input.
• AO – Analog output.

Note: Digital signals are not 5V tolerant. The voltage range is 1.6V to 3.6V.

MII SIGNALS

MII Receive Signals

MII / RMII Signals

LED Signals

Management Signals

BOOT STRAP CONFIGURATION INPUTS

GENERAL SIGNALS

10/100 LINE INTERFACE

ANALOG REFERENCES

POWER SIGNALS

ARCHITECTURE DETAILS

Top-Level Functional Architecture

The LAN8700/LAN8700i PHY is organized into the following functional blocks:

• 100BASE-TX Transmit and Receive: Handles all 100 Mbps data transmission and reception.
• 10BASE-T Transmit and Receive: Handles all 10 Mbps data transmission and reception.
• MII / RMII Interface: Provides connectivity to the Ethernet controller using either the standard Media Independent Interface (MII) or Reduced Media Independent Interface (RMII).
• Auto-Negotiation: Automatically determines the optimal speed and duplex mode for communication.
• Management Control: Enables reading of status registers and writing to control registers for configuration and monitoring.

100BASE-TX DATA PATH

100BASE-TX DATA PATH

100BASE-TX Transmit

The 100BASE-TX transmit data path is illustrated in Figure 4-1. Key functional blocks are described below.

100M Transmit Data Across the MII/RMII Interface

• MII Mode: The MAC controller places transmit data on the TXD bus and asserts TX_EN to indicate valid data. The PHY latches the data on the rising edge of TX_CLK. The data width is 4 bits at 25 MHz.
• RMII Mode: The MAC controller drives transmit data onto the TXD bus and asserts TX_EN to indicate valid data. The PHY latches the data on the rising edge of REF_CLK. The data width is 2 bits at 50 MHz.

4B/5B Encoding

• The transmit data is passed from the MII block to the 4B/5B encoder, which converts 4-bit nibbles into 5-bit symbols (code-groups).
• Out of 32 possible code-groups, 16 represent standard data (hexadecimal 0–F), while the remaining 16 are reserved for control or invalid codes (e.g., /I/ for IDLE, /H/ for Transmit Error).
• Encoding Bypass: The 4B/5B encoding can be bypassed by clearing bit 6 of register 31. In bypass mode, the 5th transmit bit carries the TX_ER signal.
• Important: Encoding can only be bypassed when the MAC interface is operating in MII mode.

Conclusion

The 100BASE-TX transmit path ensures reliable high-speed data transfer through precise MII/RMII interfacing and robust 4B/5B encoding. Its flexible design, including the option to bypass encoding in MII mode, provides adaptability for different system requirements.