DESCRIPTION

· The ispClock 5600 Family is an in-system programmable, zero-delay clock generator with a universal fan-out buffer.

· It supports input/output operations ranging from 10MHz to 320MHz.

· The device is available in 100-pin and 48-pin TQFP packages.

· It operates in commercial (0 to 70°C) and industrial (-40 to 85°C) temperature ranges.

FEATURES

· Low output to output skew (<50ps) and low jitter peak-to-peak (<60ps).

· Up to 20 programmable fan-out buffers with programmable output standards and individual enable controls.

· Fully integrated high-performance PLL with programmable lock detect and on-chip loop filter.

· Precision programmable phase adjustment per output with 16 settings and a skew range of up to +/- 12ns.

· Supports up to five clock frequency domains and flexible clock reference and external feedback inputs.

· Four user-programmable profiles stored in E2CMOS memory and full JTAG boundary scan test in-system programming support.

APPLICATIONS

· Circuit board common clock generation and distribution.

· PLL-based frequency generation.

· High fan-out clock buffer.

· Zero-delay clock buffer.