DESCRIPTION

· The ispClock 5600A Family is an in-system programmable, enhanced zero-delay clock generator with a universal fan-out buffer.

FEATURES

· Operates at 8MHz to 400MHz input/output.

· Low output-to-output skew (<50ps) and low jitter peak-to-peak.

· Supports up to 20 programmable fan-out buffers with various output standards and individual enable controls.

· Programmable output impedance (40 to 70 Ω in 5 Ω increments) and slew rate.

· Features up to 10 banks with individual V CCO and GND (1.5V, 1.8V, 2.5V, 3.3V).

· Integrated high-performance PLL with programmable lock detect and on-chip loop filter.

· Precision programmable phase adjustment per output with 16 settings and up to +/- 12ns skew range.

· Supports up to five clock frequency domains and flexible clock reference and external feedback inputs.

· All inputs and outputs are hot socket compliant.

· Includes four user-programmable profiles stored in E2CMOS memory.

· Full JTAG boundary scan test in-system programming support.

· Available in commercial (0 to 70°C) and industrial (-40 to 85°C) temperature ranges.

· Offered in 100-pin and 48-pin TQFP packages.

APPLICATIONS

· Circuit board common clock generation and distribution.

· PLL-based frequency generation.

· High fan-out clock buffer.

· Zero-delay clock buffer.