DESCRIPTION

· The 74ALVCH16373 is a 16-bit D-type transparent latch with bus hold inputs and 3-state outputs.

· It can function as two 8-bit transparent latches or a single 16-bit transparent latch.

· Features two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8 bits.

· When nLE is HIGH, data at the inputs enter the latches; when LOW, the latches store the information.

· A HIGH on nOE causes the outputs to assume a high-impedance OFF-state.

· Fully specified for partial power down applications using IOFF.

FEATURES

· Wide supply voltage range from 1.2 V to 3.6 V.

· CMOS low power dissipation.

· MULTIBYTE™ flow-through standard pin-out architecture.

· Low inductance multiple VCC and GND pins for minimum noise and ground bounce.

· Direct interface with TTL levels.

· All data inputs have bus hold.

· Latch-up performance exceeds 100 mA per JESD78 Class II.A.

· Output drive capability 50 Ω transmission lines at 85 °C.

· Current drive ±24 mA at VCC = 3.0 V.

· Complies with JEDEC standards: JESD8-7, JESD8-5, JESD8C/JESD36.

· ESD protection: HBM exceeds 2000 V, CDM exceeds 1000 V.

· Specified from -40 °C to +85 °C and from -40 °C to +125 °C.

APPLICATIONS

· Suitable for partial power down applications.

· Ideal for systems requiring low power dissipation and noise reduction.

· Used in environments requiring direct TTL level interface.

· Applicable in systems needing robust latch-up performance and ESD protection.