DESCRIPTION

· The 74AUP1T97 is a configurable multiple function gate with level translating and Schmitt-trigger inputs.

· It can be configured as MUX, AND, OR, NAND, NOR, inverter, and buffer using a 3-bit input.

· Supports direct connection of inputs to VCC or GND.

· Features low threshold Schmitt trigger inputs for 1.8 V logic levels in 3.3 V applications.

· Ensures low static and dynamic power consumption across a VCC range of 2.3 V to 3.6 V.

· Fully specified for partial power down applications with IOFF circuitry to prevent backflow current.

FEATURES

· Wide supply voltage range: 2.3 V to 3.6 V.

· CMOS low power dissipation and high noise immunity.

· Overvoltage tolerant inputs up to 3.6 V.

· Low noise overshoot and undershoot < 10% of VCC.

· IOFF circuitry for partial power-down mode operation.

· Latch-up performance exceeds 100 mA per JESD 78 Class II.

· Low static power consumption: ICC = 1.5 μA (maximum).

· Complies with multiple JEDEC standards.

· ESD protection: HBM exceeds 5000 V, CDM exceeds 1000 V.

· Multiple package options available.

· Specified temperature range: -40 °C to +125 °C.

APPLICATIONS

· Suitable for low-power and high-noise immunity applications.

· Ideal for use in systems requiring voltage level translation.

· Effective in partial power-down mode operations.

· Applicable in environments with overvoltage conditions up to 3.6 V.

· Useful in designs requiring low noise and minimal overshoot/undershoot.

· Appropriate for systems adhering to JEDEC standards for voltage levels.

· Suitable for applications requiring robust ESD protection.

· Versatile for various temperature environments from -40 °C to +125 °C.