DESCRIPTION

· The 74LVC162373A and 74LVCH162373A are 16-bit D-type transparent latches with 30 Ω termination resistors and 3-state outputs.

· The 74LVCH162373A features separate D-type inputs with bus hold for each latch.

· Both devices can function as two 8-bit transparent latches or a single 16-bit transparent latch.

· They include two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8 bits.

· Inputs can be driven from either 3.3 V or 5 V devices, making them suitable for mixed voltage environments.

· Schmitt-trigger action at all inputs ensures tolerance to slower input rise and fall times.

· Fully specified for partial power down applications using IOFF circuitry.

FEATURES

· Overvoltage tolerant inputs up to 5.5 V.

· Wide supply voltage range from 1.2 V to 3.6 V.

· CMOS low power consumption.

· Multibyte flow-through standard pinout architecture.

· Multiple low inductance supply pins for minimum noise and ground bounce.

· Direct interface with TTL levels.

· All data inputs have bus hold (74LVCH162373A only).

· IOFF circuitry provides partial Power-down mode operation.

· Complies with JEDEC standards: JESD8-7A, JESD8-5A, JESD8-C/JESD36.

· ESD protection: HBM exceeds 2000 V, CDM exceeds 1000 V.

· Specified from -40 °C to +125 °C.

APPLICATIONS

· Suitable for use in mixed 3.3 V and 5 V environments as voltage translators.

· Ideal for applications requiring low power consumption and noise reduction.

· Useful in systems needing robust ESD protection and reliable operation over a wide temperature range.

· Applicable in designs requiring partial power down mode operation.