AT91R40008-66AU-999 Model Information

Overview

The AT91R40008-66AU-999 is a high-performance microcontroller from the Atmel AT91 16/32-bit microcontroller family, based on the ARM7TDMI processor core. It offers a combination of powerful processing capabilities, extensive memory options, and versatile peripheral interfaces, making it suitable for a wide range of embedded control applications.

Features

• Processor Core: ARM7TDMI® ARM® Thumb® Processor CoreHigh-performance 32-bit RISC architectureHigh-density 16-bit instruction setLeader in MIPS/WattLittle-endianEmbeddedICE™ (In-circuit Emulation)
• Memory:256K Bytes of On-chip SRAM32-bit Data BusSingle-clock cycle access
• External Bus Interface:Fully programmableMaximum external address space of 64M BytesUp to eight chip selectsSoftware programmable 8/16-bit external data bus
• Interrupt Controller:Eight-level priority, individually maskable, vectored interrupt controllerFour external interrupts, including a high-priority, low-latency interrupt request
• I/O and Peripherals:32 programmable I/O linesThree-channel 16-bit Timer/CounterTwo USARTs with dedicated Peripheral Data Controller (PDC) channelsProgrammable Watchdog Timer
• Power-saving Features:CPU and peripheral can be deactivated individuallyFully static operation: 0 Hz to 75 MHz internal frequency range at VDDCORE = 1.8V, 85°C
• Operating Conditions:I/O operating range: 2.7V to 3.6VCore operating range: 1.65V to 1.95VTemperature range: -40°C to +85°C
• Packaging:100-lead LQFP Package (Green)

Pin Configuration

The AT91R40008-66AU-999 is available in a 100-lead LQFP package. The pin configuration includes:

• Address Bus (A0 - A23)
• Data Bus (D0 - D15)
• Chip Selects (NCS0 - NCS3, CS4 - CS7)
• Write Signals (NWR0, NWR1)
• Read Signals (NRD, NWE, NOE)
• Byte Selects (NUB, NLB)
• Wait Signal (NWAIT)
• Boot Mode Select (BMS)
• Interrupt Requests (FIQ, IRQ0 - IRQ2)
• Timer I/O Pins (TCLK0 - TCLK2, TIOA0 - TIOA2, TIOB0 - TIOB2)
• USART Pins (SCK0 - SCK1, TXD0 - TXD1, RXD0 - RXD1)
• Parallel I/O Lines (P0 - P31)
• Watchdog Overflow (NWDOVF)
• Master Clock (MCKI, MCKO)
• Reset (NRST)
• Tri-state Mode Select (NTRI)
• JTAG/ICE Debug Pins (TMS, TDI, TDO, TCK)
• Power and Ground Pins (VDDIO, VDDCORE, GND)

Architectural Overview

The AT91R40008-66AU-999 integrates the ARM7TDMI processor core with EmbeddedICE, on-chip memories, and peripherals. The architecture includes:

• Buses:Advanced System Bus (ASB) for high-performance memory accessAdvanced Peripheral Bus (APB) for low-power peripheral access
• Memories:256K bytes of internal SRAM, directly connected to the 32-bit data bus, single-cycle accessible
• Peripherals:External Bus Interface (EBI) for connecting external memories and peripheralsPower-saving module for idle mode and independent peripheral clock controlAdvanced Interrupt Controller (AIC) with 8-level priority and auto-vectoringParallel Input/Output Controller (PIO) for controlling up to 32 I/O linesWatchdog (WD) for preventing system lock-upSpecial Function (SF) module for chip identification, reset status, and protect mode

Peripherals

• USARTs:Two full-duplex, universal synchronous/asynchronous receiver/transmittersEach USART has its own baud rate generator and two dedicated PDC channelsData format includes start bit, up to 8 data bits, optional parity bit, and up to 2 stop bits
• Timer/Counter:Three 16-bit Timer/Counter channelsSupports frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation
• Power-saving:Optimizes power consumption by stopping the ARM7TDMI clock (Idle mode) and enabling/disabling peripheral clocks individually

Ordering Information

• Package Type: LQFP 100
• Operation Range: Industrial (-40°C to 85°C)
• Ordering Code: AT91R40008-66AU

Documentation and Support

For detailed information on the AT91R40008-66AU-999, refer to the associated documentation available on the Atmel website:

• ARM7TDMI (Thumb) Datasheet
• AT91x40 Series Datasheet
• AT91R40008 Electrical Characteristics
• AT91R40008 Summary Datasheet