DESCRIPTION

· The CY23S09 and CY23S05 are low-cost 3.3V zero-delay buffers designed for high-speed clock distribution.

· CY23S09 is available in a 16-pin SOIC package, while CY23S05 is an 8-pin version.

· Both devices feature on-chip PLLs that lock to an input clock on the REF pin, with feedback obtained from the CLKOUT pad.

· The PLLs enter a power-down mode when no rising edges are detected on the REF input, reducing current draw to less than 12.0 µA for commercial and 25.0 µA for industrial temperature devices.

· Multiple devices can distribute the same input clock with guaranteed skew and jitter performance.

FEATURES

· Operating range from 10 MHz to 100 MHz and 133 MHz, compatible with CPU and PCI bus frequencies.

· Zero input-output propagation delay and multiple low-skew outputs.

· Output-output skew less than 250 ps and device-device skew less than 700 ps.

· CY23S05 drives five outputs, while CY23S09 drives nine outputs grouped as 4 + 4 + 1.

· Less than 200 ps cycle-to-cycle jitter and test mode to bypass PLL (CY23S09 only).

· Available in space-saving 16-pin SOIC, 4.4 mm TSSOP (CY23S09), or 8-pin SOIC package (CY23S05).

· 3.3V operation using advanced 0.65 µm CMOS technology.

APPLICATIONS

· High-speed clock distribution in systems requiring low skew and jitter.

· Compatible with CPU and PCI bus frequencies, suitable for computing and communication systems.

· Systems requiring multiple synchronized clock outputs with minimal propagation delay.

· Applications needing power-efficient clock distribution with power-down mode capability.