DESCRIPTION

· ISSI's 512Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture.

· All inputs and outputs signals refer to the rising edge of the clock input.

· Organized as 8M x 16 x 4 banks or 16M x 8 x 4 banks.

· Available in 54-pin TSOP-II and 54-ball TF-BGA packages.

FEATURES

· Clock frequency: 200, 166, 143 MHz.

· Fully synchronous; all signals referenced to a positive clock edge.

· Internal bank for hiding row access/precharge.

· Power supply: Vdd/Vddq = 2.3V-3.6V.

· LVTTL interface.

· Programmable burst length and sequence.

· Auto Refresh (CBR) and Self Refresh.

· 8K refresh cycles every 64 ms.

· Random column address every clock cycle.

· Programmable CAS latency (2, 3 clocks).

· Burst read/write and burst read/single write operations capability.

· Burst termination by burst stop and precharge command.

· Temperature Range: Commercial (0oC to +70oC), Industrial (-40oC to +85oC), Automotive, A1 (-40oC to +85oC), Automotive, A2 (-40oC to +105oC).

APPLICATIONS

· High-speed data transfer systems.

· Systems requiring synchronous DRAM with pipeline architecture.

· Applications needing programmable burst length and sequence.

· Systems with LVTTL interface requirements.

· Environments with varying temperature ranges.