DESCRIPTION

· 28-bit 1:2 configurable registered buffer for DDR2 operation.

· Operates at 1.7V to 1.9V VDD.

· Inputs compatible with JEDEC SSTL_18 standard, except CSGEN, C, and RESET which are LVCMOS.

· Outputs optimized for unterminated DIMM loads, meeting SSTL_18 specifications, except QERR which is open-drain.

· Supports low-power standby operation.

· Includes parity checking function with QERR output.

· RESET input is asynchronous to CLK and CLK.

FEATURES

· Differential clock operation (CLK and CLK).

· Data registered at CLK high and CLK low crossing.

· RESET disables differential input receivers and resets registers.

· Parity checked on PAR_IN input, QERR generated two cycles after data.

· Even parity convention.

· C input controls pinout configuration (Register-A or Register-B).

· Low-power active operation monitored by DCS0, DCS1, and CSGEN inputs.

· VREF pins internally connected; only one needs external connection.

APPLICATIONS

· DDR2 RDIMM applications.

· Memory buffer solutions.

· Low-power system designs.

· Parity error detection systems.