SLG46538-AP Datasheet Summary

1. Overview

The SLG46538 is a highly versatile programmable mixed-signal matrix from Renesas’ GreenPAK family, integrated with an asynchronous state machine and dual-supply capability. It enables users to implement diverse mixed-signal functions in a compact, low-power single IC by programming one-time Non-Volatile Memory (NVM) to configure interconnect logic, I/O pins, and macrocells. The dual-supply feature (VDD​ and VDD2​) supports interfacing two independent voltage domains, facilitating level translation and cross-domain mixed-signal designs.

2. Key Features

2.1 Core Capabilities

• Dual-Supply Operation: VDD​ and VDD2​ range from 1.8 V (±5%) to 5 V (±10%), with VDD2​≤VDD​
• Mixed-Signal Macrocells: 4 analog comparators (ACMP), 2 voltage references (Vref), 19 combination function macrocells (LUTs, DFFs, counters/delays, etc.)
• State Machine: 8 states with flexible input logic for state transitions
• Serial Communication: I2C protocol compliance
• Memory: 8-byte RAM (I2C-readable/writable) + OTP user memory
• Oscillators: Configurable 25 kHz/2 MHz RC oscillator, 25 MHz RC oscillator, and crystal oscillator
• Additional Functions: Programmable delay, edge detectors, deglitch filters, inverter, analog temperature sensor

2.2 Environmental & Compliance

• Operating Temperature Range: -40 °C to 85 °C
• Storage Temperature Range: -65 °C to 150 °C
• RoHS Compliant / Halogen-Free
• ESD Protection: 2000 V (Human Body Model), 500 V (Charged Device Model)
• Moisture Sensitivity Level: 1

3. Package Options

• Tape and Reel (3k units) is the default shipping format; "TR" suffix is legacy and no longer used.

4. Pin Description

4.1 Power Pins

• VDD​: Primary power supply (Pin 1 for STQFN-20, Pin 16 for MSTQFN-22)
• VDD2​: Secondary power supply (Pin 14 for STQFN-20, Pin 12 for MSTQFN-22)
• GND: Ground (Pin 11 for STQFN-20, Pin 20 for MSTQFN-22)

4.2 Key I/O Pins

• General Purpose I/O (IO0-IO17): Support digital/analog input/output, with options for Schmitt trigger, low-voltage input, push-pull/open-drain output
• Special Function Pins:

4.3 Pin Configuration Notes

• IO0 is input-only; all other IOs support bidirectional operation
• IOs 0-8 are powered by VDD​; IOs 9-17 are powered by VDD2​
• Pull-up/pull-down resistors (10 kΩ/100 kΩ/1 MΩ) are configurable for all IOs (IO0 has fixed pull-down)

5. Electrical Specifications

5.1 Absolute Maximum Ratings

5.2 Typical Electrical Characteristics (3.3 V VDD​)

5.3 I2C Specifications

• Clock Frequency (FSCL​): Up to 400 kHz
• Clock Low Pulse Width (tLOW​): 1300 ns min.
• Clock High Pulse Width (tHIGH​): 600 ns min.
• Data Setup Time (tSU_DAT​): 100 ns min.

6. User Programmability

6.1 Configuration Flow

1. Design creation in GreenPAK Designer software
2. Emulation (on-chip, no NVM programming) for rapid testing
3. NVM programming with GreenPAK development tools for samples
4. Production integration by forwarding design files to Renesas

6.2 Non-Volatile Memory (NVM)

• One-Time-Programmable (OTP) for permanent configuration
• Emulation mode retains configuration while powered, supporting re-writes
• User-defined initial values for RAM are transferred from OTP during startup

7. Macrocell Details

7.1 Combination Function Macrocells

7.2 Analog Comparators (ACMP)

• Input Voltage Range: 0 to VDD​ (positive), 0 to 1.2 V (negative)
• Hysteresis Options: 0 mV/25 mV/50 mV/200 mV
• Gain Options: 1x/0.5x/0.33x/0.25x
• Wake & Sleep control for power saving

7.3 State Machine

• 8 configurable states with user-defined transitions
• 24 input signals for state transitions + 1 reset input
• 8 output signals (user-programmable per state)
• Asynchronous operation (no clock required)

7.4 Oscillators

8. Memory

8.1 RAM

• 8-byte capacity, readable/writable via I2C
• Retains data during operation; initial values from OTP

8.2 OTP Memory

• Stores user configuration (macrocells, connection matrix)
• Transfers initial RAM values during power-up
• Read-back protection (Read Lock) available

9. Applications

• Personal Computers and Servers
• PC Peripherals
• Consumer Electronics
• Data Communications Equipment
• Handheld and Portable Electronics

10. Ordering Information

11. Key Design Considerations

• VDD2​ must not exceed VDD​ at any time
• ACMP power-up time should be accounted for in timing-sensitive designs
• I2C protection bits (reg<1832>, reg<1870>, reg<1871>) control read/write access to registers
• Crystal oscillator requires external components (capacitors/resistors) for stability